110年 - 110台灣聯合大學系統_碩士班招生考試_電機類:計算機系統(計算機組織)#104945

(a) (2%) Stall cycles due to mispredicted branches increase the CPI. What is the extra CPI due to mispredicted branches with the always-taken predictor? Assume that branch outcomes are determined in the EX stage, that there are no data hazards, and that no delay slots are used.

(b) (2%) Repeat (a) for the "'always-not-taken" predictor.

(c) (2%) Repeat (a) for the 2-bit predictor.

(d) (2%) With the 2-bit predictor, what speedup would be achieved if we could convert half of the branch instructions in a way that replaces a branch instruction with an ALU instruction? Assume that correctly and incorrectly predicted instructions have the same chance of being replaced.

(e)(2%) Some branch instructions are much more predictable than others. If we know that 80% of all executed branch instructions are easy-to-predict loop-back branches that are always predicted correctly, what is the accuracy of the 2-bit predictor on the remaining 20% of the branch instructions?

(a) (2%) What is the clock cycle time in a pipelined and non-pipelined processor?

(b) (2%) If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor?

(c) (2%) Assuming there are no stalls or hazards, what is the utilization of the data memory?

(d) (2%) Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit? 300ps 100ps

(a) (2%) Consider a datapath similar to the one in the textbook shown below, but for a processor that only has one type of instruction: unconditional PC-relative branch. What would the cycle time be for this datapath?

(b) (2%) Repeat (a), but this time we need to support only conditional PC-relative branches. The remaining three problems refer to the datapath element Shift-left-2:

(c) (2%) For which kind of instructions (if any) requires this resource on the critical path?

(d) (2%) Assuming that we only support beg and add instructions, discuss how changes in the given latency of this resource affect the cycle time of the processor. Assume that the latencies of other resources do not change.

(a) (4%) How would this affect the size of each of the bit fields in the R-type, and I-type, respectively, instructions?

(b) (4%) How could each of the two proposed changes decrease the size of an MIPS assembly program? On the other hand, how could the proposed change increase the size of an MIPS assembly program?

5. (12%) Translate the following C code to MIPS assembly code. Please use a minimum number of instructions. Assume that the values of a, b, i and j are in registers $s0, $s1, $to, and $t1, respectively. Also, assume that register Ss2 holds the base address of the array D.

6. (4%) SISD, SIMD, MISD, and MIMD are one categorization of parallel hardware architectures proposed in the 1960s and still used today. What are SISD, SIMD, MISD, and MIMD? Please give a brief explanation and one example for each architecture.

(a) [3%] What is the CPI for M1 and M2?

(b) [3%] What is the MIPS rating for?

(c) [3%] A favorite program runs in 10 seconds on machine M1. If we want to build a new machine M3, which will run this program in 6 seconds. But it require 1.2 times as many clock cycles as M1 for this program. What is the clock rate of M3?

(a) [3%] Assume 185 and 169 are signed 8-bit decimal integers store in sign-magnitude format. Calculate 185+169. The result should be written in decimal.

(b) [3%] Assume 185 and 169 are signed 8-bit decimal integers store in two's complement format. Calculate 185+169. The result should be written in decimal.

(c) [3%] What decimal number does the bit pattern Ox0E000000 represent if it is a floating point number? Use the IEEE 754 standard.

(d) [4%] Calculate the binary number (1.1100)*(-0.1101) step by step. You should use guard, round and sticky bit in rounding step. The result should store in IEEE 754 with 5 bits mantissa.

(a) [3%] What is the block size (in words) of each case?

(b) [3%] For the total of two cases, how many entries does the cache have??

Starting from power on, the following byte-addressed cache references are recorded.

(c) [3%] For Case I, how many blocks are replaced?

(d) [3%] For Case I, what is the hit ratio?

(e) [4%] For Case I as the final state of the cache, how many valid entries in this cache? Show the index for each valid entry. Case I

(a) [3%] Assume the miss rate of an instruction cache is 2% and the miss rate of the data cache is 4%, If a processor has a CPI of 2 without any memory stalls and the miss penalty is 200 cycles for all misses. Assume the frequency of all loads and stores is 36%. Determine how much faster a processor would run with a perfect cache that never missed.

(b) [3%] If the processor has a base CPI of 1, and clock rate of 4 GHz. Assume the memory access time is 100 ns, including al the miss handling. Suppose the miss rate per instruction at the primary cache is 3%. Now we add a secondary data cache that has a 5 ns access time for either a hit or a miss, and is large enough to reduce the miss rate to main memory to 0.5%. What is the total CPI of this two-level cache?

(a) [3%] For a single-level page table, how much physical memory is needed for storing the page table?

(b) [3%] In a memory hierarchy system, we can integrate virtual memory, TLB and cache. A memory reference can encounter three different types of misses: a TLB miss, a page fault and a cache miss. Considering all the combinations of these three events with one or more occurring. Identify the number for the three events which is impossible.

110年 - 110台灣聯合大學系統_碩士班招生考試_電機類:計算機系統(計算機組織)#104945

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