所屬科目:中山◆資工◆計算機結構
4. Identify all of the data dependencies in the following code running in a 5-stage pipelined MIPS CPU. Which dependencies are data hazards that will be resolves via forwarding? Which dependencies are data hazards that will cause a stall? strategy.
6. Given the following datapath for the single-cycle implementation of a computer and thedefinition of its instructions:
Assume that the instructions are fixed length and the operation time for the major functional units in
this implementation are as follows:
●Memory units: 2ns
●ALU and adders: 2ns
●Register file (read or write): 1ns
●Multiplexers, control unit, PC accesses, sign extension unit, and wires: no delay
Please compute the required time for each instruction and explain why.