108年 - 108 國立中山大學_碩士班招生考試_資工系(甲、乙組)：計算機結構#105762

1.1 What is the binary representation of zero in the singie-precision format? Express your ans using binary format similar to x_xoxooooz xcxcocxxxxcxxc xxxexxrxrr where x is eit ither O or 1.

1.2 What is the binary represent ntation of the decimal value -0.5 in single precision format?

1.3 What is the maximum magnitude of ordinary numbers (i.e, excluding intinity, NaN, and subnormal numbers) in single precision floating-point representation? Express your answer in format of x.xx.ㆍㆍㆍxx× where x ∈ (0,IJ and e is the decimal value of the exponent.

1.4 What is the minimum magnitude of ordinary numbers (i.e, other than zero) in single precision foating-point representation? Express your answer in format of x..cx---xx× where x∈ (0,1) and e is the decimal value of the exponent.

1.5 What is the minimum magnitude of subnormal numbers in single precision floating-point represcntation? Express your answer in format of x..xx...xx× where x ∈ [0,1J and e is the decimal value of the exponent.

1.6 What is the representable range of the single-precision floating-point numbers?

1.7 Is the distance between two neighboring singlo-precision foating-point numbers the same?

1.8 For a 32-bit two's complement signed fixed-point rep presentation with 16 integer bits and 16 fractional bits, is the distance between two neighboring numbers the same? Why?

1.9 Continued with the previous 32-bit signed fixed-point representation, what is the representable range of the 32-bit signed fixed-point format?

1.10 In general, addition of two 32-bit fixed-point numbers can be finished in one clock cycle. However, addition of two single-precision floating-point numbers usually takes more than one clock cycle. Why? Hint: explain using the operations involved in floating-point addition/subtraction. Why?

2.

2.1 A processor is busy with computation 40% of aputation 40% of the execution time, and is waiting for I/O access 60% of the execution time. If we replace the processor with a new one which is 10 times faster than the old processor, what is the overall speedup gained using the new processor assuming that the percentage of IO access remains the same in both processors?

2.2 If you want to achieve a speedup of 80 for a computation task using 100 processots running concurrently, what faction of the computation task can be sequential according to Amdahl's law?

2.3 For an application program running on a multi-processor system with 32 processors, it takes 200 ns to handle reference in a remote memory. Assume that this application program always bas hits in the local mem nory except for remote memor ry access involving commun nication. Proc cessors are stalled on a remote request, and the processor clock is 3.3 GHz. Assume that the base CPI (cycles per instruction) is 0.5 and all references hit in cache. How much faster is the multi-processor if there is no communicatio ion versus if 0.2% of instructions s involve remote e communication. references? Hint: compute the new CPI first. The speedup is the ratio of the two CPI values.

2.4 Assume that 25% operations of a computation task are floating-point operations and average CPI (cycles per instruction) for floating-point operations and other operations are 4.0 and 1.33 respectively. Sup ppose that 2% of the floating-poi operations in the task are floating- -point division which has CPI = 20. Assume that the two design altemnatives are to decrease the CPI of the foating- point division to 2 or the decrease the average CPI of all floating-point operations to 2.5. Compare these two design alternatives using processor performance equation. Which design choice is better? Why? Hint: compute the CPI values of different designs. e the floating-point

3.1 What is the maximun m working frequency of the above CPU?

3.2 Assume that a computation task contains only 100 instructions and there is no hazard for these instructions, what is the throughput of this task? What is the total latency of finishing executing this task? What is the average cycle per instruction (CPI) in this task?

3.3 If we want to reduc ce the pi pipelined stages from 5 to 4 by merging some of the five types of pipelined operations mentioned above, what is the best design if the spced performance is the first choice? And what is the maximun working frequency of the new design with four pipelined stages?

3.4 What is data hazard? Give an assembly language example to show one type of data hazard.

3.5 What is super-pipeline? What are the advantages and disadvantages of super-pipeline design?

4.2 Repeat the above problem for a two-way set-associative cache.

4.3 Repeat the above problem for a fully associative cache.

4.4 Compare the advantages and disadvantages of the above three different cache designs. Which one is usually used in the design of TLB (translati ation lookaside buffer)? Why?

4.5 The average mem mory access time (AMAT) per instruction can be expressed as AMAT = time for a hit + miss rate *miss penalty Find the AMAT for a processor with a 1ns clock cycle time, a miss penalty of 20 clock cycles, a miss rate of 0.05 miss sses per er instru uction, and a cache ac access time (including hit detection) of 1 clock cycle. Assume that the read and write miss penalties are the sarre and ignore other write stalls.

4.6 Assume the miss rate of an instruction cache is 2% and the miss rate of the data cache is 4%. If 100 cycles for all misses, de etermine how m a processor has a CPI (cycle per instruction) of 2 without any memory stalls and the miss penalty is much faster a proce cessor would run with a perfect cache that never missed. Assue the frequency of all loads and stores is 36%.

4.7 Suppose that in 1000 memory references, there are 40 misses in the first-level cache and 20 misses in the second-1 level cache. Assume the miss pen nalty from L2 cache to memo ory is 200 clock cycles, the hit time of L2 cache is 10 clock cycles, and the hit time of Ll cache is 1 clock cycle. What is the average memory y access time? Hint: average memory access time = LI_hit_time + Ll miss rate * ( 12 hit time + L2 local_miss_rate * * L2 miss penalty ) where the 12 local miss_rate is the nunber of misses in L2 cache divided by the total numnber of memory accesses to L2 cache.

4.8 Continued with the previous problem, and assuming that there is 1.5 memory references per instruction, what are the average stall cycles per instructions? Hint: average memory stall pet instruction = Ll_misses _per_instruction L2 hit time + L2 misses per _instruction 12 _miss_penaity

5. 5.1 What is the advantage of single instruction multiple data (SIMD)? Compare the differences between SIMD in conventional CPU (Central Processing Units) and SIMD in GPU (Graphics Processing Units)

5.2 What is control hazard? Propose a method to improve the performance degradation due to control hazard.

5.3 What are the differences of spatial locality and temporal locality during execution of computation tasks in CPU? Give two programming techniques to explain the differences.

5.4 What is static multiple issue? What is dynamic multiple issue? Compare the differences.

108年 - 108 國立中山大學_碩士班招生考試_資工系(甲、乙組)：計算機結構#105762

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