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110年 - 第二章全方位的全民國防---全民國防的意涵(幼獅)申論題#106028
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3.國防建設的強化不能只靠硬體的軍備武器,還包含何者更重要的基礎?
詳解 (共 2 筆)
繼續努力!
詳解 #5378843
2022/03/14
精神戰力國防共識
(共 10 字,隱藏中)
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mkmkmk
詳解 #5416122
2022/04/13
國防建設不能只靠硬體的軍備武器,精神戰力...
(共 35 字,隱藏中)
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4.各地方政府依據過去臺灣戰爭歷史的描述打造文物園區,目的為何?
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5.擴大國防安全基礎、增強國防武力的最終目標為何?
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(a) [5 points] Please write a C code to implement the convolution function in our case study. Please make sure that your code is comprehensive with sufficient comments.
#452370
(b) [5 points] Please convert your C code to an assembly code. No optimization is needed here. You can use any instruction set architecture, but please make sure that your code is comprehensive with sufficient comments.
#452371
(c) [5 points] Suppose that we have a simple 5-stage pipelined processor here. The pipeline stages are IF (instruction fetch), ID (instruction decode/register), EX (execution), MEM (memory), and WB (write-back), as shown in the figure below. The pipeline is in-order issue and in-order execution with ideal one cycle-per-instruction (CPD). It executes a branch instruction in the EX stage. It can detect hazards, but does not support forwarding between pipeline stages.
#452372
(d) [5 points] To improve the pipeline performance in the previous question, we would like to reduce the impact of control hazards by adding branch prediction to the processor pipeline. Please describe how this can be done and how it affects the performance.
#452373
(e) [5 points] To further improve the pipeline performance in the previous question, we would like to reduce the impact of data hazards by unrolling the loop. Please describe how this can be done and how it affects the performance.
#452374
(f) [5 points] Now, let us take the data memory into consideration. Assume each memory access takes 10 cycles, and there is a processor data cache to speed up the memory access for reused data. If an access hits the data cache, then the processor would not stall. Suppose the data cache is a direct-mapped cache which has 16 blocks and each block has 16 bytes. Estimate the data cache miss rates for M=1, 4, and 8.
#452375
(g) [5 points] Can "blocking" be used to reduce the cache misses in the previous question? If yes, please rewrite the code with blocking and estimate the performance benefit of blocking.
#452376
(h) [5 points] Suppose we want to apply the same convolution kernel to many independent input sequences, can we take advantage of multithreading to increase the performance? Please describe how such multithreading can be done, or why it cannot be done.
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